The present invention relates to a semiconductor memory including a ferroelectric capacitor and a method for driving the same.
A first known example of a semiconductor memory including a ferroelectric capacitor is composed of, as shown in FIG. 7, a field effect transistor (hereinafter referred to as the FET) 1 and a ferroelectric capacitor 2 with a drain region 1a of the FET 1 connected to a bit line BL, a source region 1b of the FET 1 connected to an upper electrode of the ferroelectric capacitor 2 and a gate electrode 1c of the FET 1 connected to a word line WL.
The semiconductor memory of the first conventional example employs the destructive read-out system in which a recorded data is erased in reading the data. Therefore, it is necessary to carry out a rewrite operation after a data read operation, and hence, an operation for reversing the polarization direction of the ferroelectric film (polarization reversing operation) should be carried out after every data read operation.
Since a phenomenon designated as polarization fatigue occurs in a ferroelectric film, the polarizing characteristic of the ferroelectric film is largely degraded when the polarization reversing operation is repeatedly carried out.
As a countermeasure, a semiconductor memory of a second conventional example as shown in FIG. 8 has been proposed. Specifically, the semiconductor memory of the second conventional example employs the non-destructive read-out system in which a lower electrode 2b of a ferroelectric capacitor 2 is connected to a gate electrode 1c of an FET 1 so as to use the ferroelectric capacitor 2 for controlling the gate potential of an FET 1. In FIG. 8, a reference numeral 3 denotes a substrate.
In writing a data in the semiconductor memory of the second conventional example, a writing voltage is applied between an upper electrode 2a of the ferroelectric capacitor 2 working as the control gate and the substrate 3.
For example, when a data is written by applying a voltage (control voltage) positive with respect to the substrate 3 to the upper electrode 2a, downward polarization is caused in a ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, positive charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has a positive potential.
When the potential of the gate electrode 1c exceeds the threshold voltage of the FET 1, the FET 1 is in an on-state. Therefore, when a potential difference is caused between a drain region 1a and a source region 1b of the FET 1, a current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory is defined, for example, as xe2x80x9c1xe2x80x9d.
On the other hand, when a voltage negative with respect to the substrate 3 is applied to the upper electrode 2a of the ferroelectric capacitor 2, upward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, negative charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has a negative potential. In this case, the potential of the gate electrode 1c is always lower than the threshold voltage of the FET 1, and hence, the FET 1 is in an off-state. Therefore, even when a potential difference is caused between the drain region 1a and the source region 1b of the FET 1, no current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory is defined, for example, as xe2x80x9c0xe2x80x9d.
Even when the power supply to the ferroelectric capacitor 2 is shut off, namely, even when the voltage application to the upper electrode 2a of the ferroelectric capacitor 2 is stopped, the aforementioned logical states are retained, and thus, a nonvolatile memory is realized. Specifically, when power is supplied again to apply a voltage between the drain region 1a and the source region 1c after shutting off the power supply for a given period of time, a current flows between the drain region 1a and the source region 1b if the logical state is xe2x80x9c1xe2x80x9d, so that the data xe2x80x9c1xe2x80x9d can be read, and no current flows between the drain region 1a and the source region 1b if the logical state is xe2x80x9c0xe2x80x9d, so that the data xe2x80x9c0xe2x80x9d can be read.
In order to correctly retain a data while the power is being shut off (which characteristic for retaining a data is designated as retention), it is necessary to always keep the potential of the gate electrode 1c of the FET 1 to be higher than the threshold voltage of the FET 1 when the data is xe2x80x9c1xe2x80x9d and to always keep the potential of the gate electrode 1c of the FET 1 at a negative voltage when the data is xe2x80x9c0xe2x80x9d.
While the power is being shut off, the upper electrode 2a of the ferroelectric capacitor 2 and the substrate 3 have a ground potential, and hence, the potential of the gate electrode 1c is isolated. Therefore, ideally, as shown in FIG. 9, a first intersection c between a hysteresis loop 4 obtained in writing a data in the ferroelectric capacitor 2 and a gate capacitance load line 7 of the FET 1 obtained when a bias voltage is 0 V corresponds to the potential of the gate electrode 1c obtained in storing a data xe2x80x9c1xe2x80x9d, and a second intersection d between the hysteresis loop 4 and the gate capacitance load line 7 corresponds to the potential of the gate electrode 1c obtained in storing a data xe2x80x9c0xe2x80x9d. In FIG. 9, the ordinate indicates charge Q appearing in the upper electrode 2a (or the gate electrode 1c) and the abscissa indicates voltage V.
Actually, however, the ferroelectric capacitor 2 is not an ideal insulator but has a resistance component, and hence, the potential of the gate electrode 1c drops through the resistance component. This potential drop is exponential and has a time constant obtained by multiplying parallel combined capacitance of the gate capacitance of the FET 1 and the capacitance of the ferroelectric capacitor 2 by the resistance component of the ferroelectric capacitor 2. The time constant is approximately 104 seconds at most. Accordingly, the potential of the gate electrode 1c is halved within several hours.
Since the potential of the gate electrode 1c is approximately 1 V at the first intersection c as shown in FIG. 9, when the potential is halved, the potential of the gate electrode 1c becomes approximately 0.5 V, which is lower than the threshold voltage of the FET 1 (generally of approximately 0.7 V). As a result, the FET 1 that should be in an on-state is turned off in a short period of time.
In this manner, although the ferroelectric memory using the ferroelectric capacitor for controlling the gate potential of the FET has an advantage that a rewrite operation is not necessary after a data read operation, it has the following problem: The gate electrode of the FET obtains a potential after writing a data, and the ability for keeping the gate potential determines the retention characteristic. Since the time constant until discharge of the ferroelectric capacitor is short due to the resistance component of the ferroelectric capacitor, the data retaining ability is short, namely, the retention characteristic is not good.
For overcoming this problem, the present inventors have considered a semiconductor memory as shown in FIG. 10. Hereinafter, the semiconductor memory of FIG. 10 set forth as a premise of the invention is designated as a premise semiconductor memory.
In a memory cell block in the first column of the premise semiconductor memory, a plurality of ferroelectric capacitors, for example, four ferroelectric capacitors CF11, CF21, CF31 and CF41 are serially connected to one another in a bit line direction, and the ferroelectric capacitors CF11, CF21, CF31 and CF41 are respectively connected to cell selecting field effect transistors (hereinafter simply referred to as the cell selecting transistors) Q11, Q21, Q31 and Q41 in parallel. Thus, each of the ferroelectric capacitor and a corresponding one of the cell selecting transistors together form a memory cell. To a lower end of a series circuit in the first column including the serially connected plural ferroelectric capacitors CF11, CF21, CF31 and CF41, a first reading field effect transistor (hereinafter simply referred to as the reading transistor) Q51 is connected for reading a data by detecting displacement of the polarization of a ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors CF11, CF21, CF31 and CF41.
Also, in a memory cell block in the second column, similarly to the first memory cell block, a plurality of ferroelectric capacitors CF12, CF22, CF32 and CF42 are serially connected to one another in the bit line direction, and the ferroelectric capacitors CF12, CF22, CF32 and CF42 are respectively connected to cell selecting transistors Q12, Q22, Q32 and Q42 in parallel. To a lower end of a series circuit in the second column including the plural serially connected ferroelectric capacitors CF12, CF22, CF32 and CF42, a second reading transistor Q52 is connected for reading a data by detecting displacement of the polarization of a ferroelectric film of a selected ferroelectric capacitor.
The gate electrodes of the cell selecting transistors Q11 and Q12 included in the memory cells disposed on the first row are connected to a first word line WL1, the gate electrodes of the cell selecting transistors Q21 and Q22 included in the memory cells disposed on the second row are connected to a second word line WL2, the gate electrodes of the cell selecting transistors Q31 and Q32 included in the memory cells disposed on the third row are connected to a third word line WL3, and the gate electrodes of the cell selecting transistors Q41 and Q42 included in the memory cells disposed on the fourth row are connected to a fourth word line WL4.
An upper end of the series circuit in the first column, namely, the upper electrode of the ferroelectric capacitor CF11 disposed on the first row, is connected to a first control line (first set line) BS1, the lower end of the series circuit in the first column, namely, the lower electrode of the ferroelectric capacitor CF41 disposed on the fourth row, is connected to the gate electrode of the first reading transistor Q51, and the drain region of the first reading transistor Q51 is connected to a first bit line BL1.
An upper end of the series circuit in the second column, namely, the upper electrode of the ferroelectric capacitor CF12 disposed on the first row, is connected to a second control line (second set line) BS2, the lower end of the series circuit in the second column, namely, the lower electrode of the ferroelectric capacitor CF42 disposed on the fourth row, is connected to the gate electrode of the second reading transistor Q52, and the drain region of the second reading transistor Q52 is connected to a second bit line BL2.
The source region of the first reading transistor Q51 and the source region of the second reading transistor Q52 are connected to a plate line (reset line) CP.
A write operation of the premise semiconductor memory will now be described. In the following description, a data is written in, for example, the ferroelectric capacitor CF21 included in the memory cell disposed in the first column and on the second row.
First, a high voltage is applied to the word lines WL1, WL3 and WL4 so as to turn on the cell selecting transistors Q11, Q31 and Q41, and a ground voltage is applied to the word line WL2 so as to turn off the cell selecting transistor Q21. In this manner, the ferroelectric capacitor CF21 is selected, and the capacitance of the ferroelectric capacitor CF21 and the gate capacitance of the first reading transistor Q51 are serially connected to each other. Therefore, one end of the series capacitance circuit is connected to the well region of the first reading transistor Q51 and the other end of the series capacitance circuit is connected to the first control line BS1.
Next, when the well region of the first reading transistor Q51 is grounded and a writing voltage is applied to the first control line BS1, the polarization direction of the ferroelectric capacitor CF21 is changed in accordance with the polarity of the writing voltage. Thereafter, when a high voltage is applied to the word line WL2 so as to turn on the cell selecting transistor Q21, the upper electrode and the lower electrode of the ferroelectric capacitor CF21 are short-circuited, resulting in resetting the ferroelectric capacitor CF21.
A read operation for reading a data from the ferroelectric capacitor CF21 included in the memory cell disposed in the first column and on the second row is carried out as follows:
First, in the same manner as in a write operation, a high voltage is applied to the word lines WL1, WL3 and WL4 so as to turn on the cell selecting transistors Q11, Q31 and Q41, and a ground voltage is applied to the word line WL2 so as to turn off the cell selecting transistor Q21. Thus, the ferroelectric capacitor CF21 is selected, and the capacitance of the ferroelectric capacitor CF21 and the gate capacitance of the first reading transistor Q51 are serially connected to each other. Therefore, one end of the series capacitance circuit is connected to the well region of the first reading transistor Q51 and the other end is connected to the first control line BS1.
Next, the well region of the first reading transistor Q51 is grounded and a reading voltage is applied to the first control line BS1. Thus, a voltage obtained by dividing the reading voltage in accordance with a capacitance ratio between the capacitance of the ferroelectric capacitor CF21 and the gate capacitance of the first reading transistor Q51 is applied to the gate electrode of the first reading transistor Q51, a current flows between the drain region and the source region of the first reading transistor Q51 in accordance with the potential of the gate electrode thereof, and the current flows between the plate line CP and the first bit line BL1.
In the premise semiconductor memory, the polarization value of a ferroelectric film is different depending upon a data written in a ferroelectric capacitor including the ferroelectric film, and hence, the change of the polarization value of the ferroelectric film caused in applying a reading voltage is also different depending upon the data. Since a ratio of the change of a polarization value to the change of a voltage corresponds to capacitance, the capacitance of a ferroelectric capacitor is different depending upon the polarization value of a ferroelectric film corresponding to a written data. In other words, the capacitance of the selected ferroelectric capacitor CF21 has a different value depending upon the polarization value of the ferroelectric film of the ferroelectric capacitor CF21.
The gate voltage of the first reading transistor Q51 is determined on the basis of capacitance division between the capacitance of the ferroelectric capacitor CF21 and the gate capacitance of the first reading transistor Q51. Therefore, the gate capacitance of the first reading transistor Q51 is changed depending upon the polarization value of the ferroelectric film of the ferroelectric capacitor CF21.
Accordingly, in accordance with a data written in the ferroelectric capacitor CF21, a value of a current flowing between the source region and the drain region of the first reading transistor Q51 is changed. When this change of the current value is detected, the data written in the ferroelectric capacitor CF21 can be read.
As described above, in the premise semiconductor memory, the ferroelectric capacitor is reset after writing a data therein, and hence, no voltage is applied to the ferroelectric capacitor during data retention time. Therefore, this semiconductor memory has a good retention characteristic. Specifically, the premise semiconductor memory can attain a good retention characteristic by retaining the polarization state of a ferroelectric film instead of retaining a potential difference caused in a ferroelectric capacitor.
In the premise semiconductor memory, however, parasitic capacitances between the respective ferroelectric capacitors and the reading transistor are different depending upon the addresses of the ferroelectric capacitors. For example, when the parasitic capacitance present between the ferroelectric capacitor CF41 on the fourth row and the first reading transistor Q51 is assumed to be q, and the parasitic capacitance of each of the cell selecting transistors Q11, Q21, Q31 and Q41 is assumed to be q1 the parasitic capacitance present in reading a data from the ferroelectric capacitor CF41 on the fourth row is q1 while the parasitic capacitance present in reading a data from the ferroelectric capacitor CF11 on the first row is q1+3xc3x97q2.
Since the parasitic capacitances present between the respective ferroelectric capacitors and the reading transistor are thus different depending upon the addresses, the gate voltage of the reading transistor is varied depending upon the address of a ferroelectric capacitor to be read in a read operation. This disadvantageously makes the operation of the reading transistor unstable.
In consideration of the aforementioned disadvantage, an object of the invention is stabilizing the operation of a reading transistor although parasitic capacitance present between each ferroelectric capacitor and a reading transistor is different depending upon the address of the ferroelectric capacitor.
In order to achieve the object, the semiconductor memory of this invention comprises a plurality of ferroelectric capacitors successively connected to one another in a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof; a plurality of selecting transistors respectively connected to the plurality of ferroelectric capacitors in parallel for selecting a selected ferroelectric capacitor from the plurality of ferroelectric capacitors; a set line connected to a first end of a series circuit including the plurality of successively connected ferroelectric capacitors, a reading voltage being applied to the set line; and a load capacitor connected to a second end of the series circuit for detecting displacement of polarization of the ferroelectric film of the selected ferroelectric capacitor, and in the series circuit, capacitance is set to be larger in a ferroelectric capacitor disposed in a position relatively near to the first end than in a ferroelectric capacitor disposed in a position relatively far from the first end.
In the semiconductor memory of this invention, in the series circuit including the plural ferroelectric capacitors, the capacitance is set to be higher in a ferroelectric capacitor disposed in a position relatively near to the end for receiving the reading voltage than in a ferroelectric capacitor disposed in a position relatively far from the end. Therefore, even through parasitic capacitances present between the ferroelectric capacitors and the reading transistor are different depending upon the addresses, a difference in the voltage applied to the load capacitor in a read operation can be reduced, so that the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor can be stably detected.
In the semiconductor memory, the capacitance of each of the ferroelectric capacitors is preferably set to be in proportion to a sum of parasitic capacitance present between the ferroelectric capacitor and the load capacitor, and capacitance of the load capacitor. For example, assuming that a first ferroelectric capacitor has capacitance Q1A, that a second ferroelectric capacitor has capacitance Q1B, that parasitic capacitance Q2A is present between the first ferroelectric capacitor and the load capacitor, that parasitic capacitance Q2B is present between the second ferroelectric capacitor and the load capacitor, and that the load capacitor has capacitance Q3, the capacitances Q1A and Q1B are preferably set so that the relationship of             Q              1        ⁢        A              /          Q              1        ⁢        B              =            (                        Q                      2            ⁢            A                          +                  Q          3                    )        /          (                        Q                      2            ⁢            B                          +                  Q          3                    )      
can hold.
When the capacitances are thus set, even when the parasitic capacitances present between the ferroelectric capacitors and the reading transistor are different depending upon the addresses, the voltage applied to the load capacitor is the same in reading a data from any of the ferroelectric capacitors. Accordingly, the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor can be very stably detected.
In the semiconductor memory, in the series circuit, one electrode having a smaller area between two electrodes of each of the plurality of ferroelectric capacitors preferably has a larger area in a ferroelectric capacitor disposed in a position relatively near to the first end than in a ferroelectric capacitor disposed in a position relatively far from the first end.
Thus, in the series circuit including the plural ferroelectric capacitors, the capacitance can be easily and definitely set to be larger in a ferroelectric capacitor disposed in a position relatively near to the end for receiving the reading voltage than in a ferroelectric capacitor disposed in a position relatively far from the end.
In the semiconductor memory, in the series circuit, the ferroelectric film preferably has a smaller thickness in a ferroelectric capacitor disposed in a position relatively near to the first end than in a ferroelectric capacitor disposed in a position relatively far from the first end.
Thus, in the series circuit including the plural ferroelectric capacitors, the capacitance can be easily and definitely set to be larger in a ferroelectric capacitor disposed in a position relatively near to the end for receiving the reading voltage than in a ferroelectric capacitor disposed in a position relatively far from the end.
In the semiconductor memory, in the series circuit, an amount of a dopant added to the ferroelectric film is preferably larger in a ferroelectric capacitor disposed in a position relatively near to the first end than in a ferroelectric capacitor disposed in a position relatively far from the first end.
Thus, in the series circuit including the plural ferroelectric capacitors, the capacitance can be easily and definitely set to be larger in a ferroelectric capacitor disposed in a position relatively near to the end for receiving the reading voltage than in a ferroelectric capacitor disposed in a position relatively far from the end.
In the semiconductor memory, the reading voltage applied to the set line is preferably set to such magnitude that a voltage applied between two electrodes of the selected ferroelectric capacitor in applying the reading voltage is not more than a coercive voltage of the selected ferroelectric capacitor.
Thus, the displacement of the polarization of the ferroelectric film can be restored to that obtained before reading a data, and hence, there is no need to carry out a rewrite operation. As a result, the fatigue characteristic of the ferroelectric capacitor can be improved.
In the semiconductor memory, the load capacitor is preferably a field effect transistor whose gate electrode is connected to the second end of the series circuit.
Thus, the displacement of the polarization of the ferroelectric film can be definitely detected by detecting a current flowing between the drain region and the source region of the field effect transistor.
The method for driving a semiconductor memory of this invention is employed in a semiconductor memory including a plurality of ferroelectric capacitors successively connected to one another in a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof; a plurality of selecting transistors respectively connected to the plurality of ferroelectric capacitors in parallel for selecting a selected ferroelectric capacitor from the plurality of ferroelectric capacitors; a set line connected to a first end of a series circuit including the plurality of successively connected ferroelectric capacitors, a reading voltage being applied to the set line; and a load capacitor connected to a second end of the series circuit for detecting displacement of polarization of the ferroelectric film of the selected ferroelectric capacitor, with capacitances of the plurality of ferroelectric capacitors being set to be equal to one another, and the method comprises a step of setting the reading voltage applied to the set line to be lower in reading a data from a ferroelectric capacitor disposed in a position in the series circuit relatively near to the first end than in reading a data from a ferroelectric capacitor disposed in a position relatively far from the first end.
In the method for driving a semiconductor memory of this invention, in the series circuit including the plural ferroelectric capacitors, the reading voltage is set to be lower in reading a data from a ferroelectric capacitor disposed in a position relatively near to the end for receiving the reading voltage than in reading a data from a ferroelectric capacitor disposed in a position relatively far from the end. Therefore, even through parasitic capacitances present between the ferroelectric capacitors and the reading transistor are different depending upon the addresses, a different in the voltage applied to the load capacitor in a read operation can be reduced. As a result, the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor can be stably detected.
In the method for driving a semiconductor memory, magnitude of the reading voltage is preferably set to be in reverse proportion to a sum of parasitic capacitance present between the selected ferroelectric capacitor and the load capacitor, and capacitance of the load capacitor. For example, assuming that a data is read from a first ferroelectric capacitor by applying a reading voltage VRA, that a data is read from a second ferroelectric capacitor by applying a reading voltage VRB, that parasitic capacitance Q2A is present between the first ferroelectric capacitor and the load capacitor, that parasitic capacitance Q2B is present between the second ferroelectric capacitor and the load capacitor, and that the load capacitor has capacitance Q3, the reading voltages VRA and VRB are preferably set so that the relationship VRA/VRB=(Q2B+Q3)/ (Q2A+Q3) can hold.
When the reading voltages are thus set, even through the parasitic capacitances present between the ferroelectric capacitors and the reading transistor are different depending upon the addresses, the voltage applied to the load capacitor is the same in reading a data from any of the ferroelectric is capacitors. As a result, the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor can be very stably detected.
In the method for driving a semiconductor memory, the reading voltage applied to the set line is preferably set to such magnitude that a voltage applied between two electrodes of the selected ferroelectric capacitor in applying the reading voltage is not more than a coercive voltage of the selected ferroelectric capacitor.
Thus, the displacement of the polarization of the ferroelectric film can be restored to that obtained before reading a data, and hence, there is no need to carry out a rewrite operation. As a result, the fatigue characteristic of the ferroelectric capacitor can be improved.
In the method for driving a semiconductor memory, the load capacitor is preferably a field effect transistor whose gate electrode is connected to the second end of the series circuit.
Thus, the displacement of the polarization of the ferroelectric film can be definitely detected by detecting a current flowing between the drain region and the source region of the field effect transistor.